Carré

dr. H.S. Bindra (Harijot Singh)

Assistant Professor
EEMCS-EE-ICD
Carré
h.s.bindra@utwente.nl
+31534895179
Business card

Expertise

  • Engineering

    • Energy Engineering
    • Front End
    • Comparator
    • Analog-to-Digital Converter
    • Sampling Technique

  • Earth and Planetary Sciences

    • Input
    • Bias
    • Latch

Organisations

Low Energy Circuit Design Techniques

Analog power consumption does not depend on supply voltage and unlike digital, doesn’t benefit from technology scaling. The focus of this research work is to investigate CMOS circuit design techniques for minimizing the energy consumption for a given analog operation.

Publications

2025

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification (2025)IEEE journal of solid-state circuits (E-pub ahead of print/First online). Ponte, J., Plompen, R., Zijlma, E., Klumperink, E. A. M., Bindra, H. S. & Nauta, B.https://doi.org/10.1109/JSSC.2025.3611114Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS (2025)IEEE journal of solid-state circuits (E-pub ahead of print/First online). Rajendra, A. K., Bindra, H. S. & Nauta, B.https://doi.org/10.1109/JSSC.2025.3612157Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption (2025)In 2025 Joint European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit): Physical Layer and Fundamentals (PHY) (pp. 643-648). IEEE. Kendae Ramkumar, V., Bindra, H. S., Klumperink, E. A. M., Abdelmagid, B. A. & Wang, H.https://doi.org/10.1109/EuCNC/6GSummit63408.2025.11036941A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture (2025)In 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (Symposium on VLSI Technology; Vol. 2025). IEEE. Cents, R., Bindra, H. S., De Vree, H. & Nauta, B.https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074903A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection (2025)IEEE journal of solid-state circuits, 60(6), 1997-2012. Article 0018-9200. Kendae Ramkumar, V., Huiskamp, M., Bindra, H. S., Klumperink, E. & Nauta, B.https://doi.org/10.1109/JSSC.2024.3481879Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals (2025)In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). IEEE. Rajendra, A. K., Freriksen, J. & Bindra, H. S.https://doi.org/10.1109/ISCAS56072.2025.11044182A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI (2025)In IEEE International Solid-State Circuits Conference 2025 (pp. 76-78). IEEE. Heel, J., Bindra, H. S., Louwsma, S., Dezzani, A. & Nauta, B.https://doi.org/10.1109/ISSCC49661.2025.10904786A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth (2025)IEEE transactions on circuits and systems I: regular papers, 72(10), 5365-5377. Ponte, J., Nauta, B. & Bindra, H. S.https://doi.org/10.1109/TCSI.2025.3536610A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI (2025)IEEE journal of solid-state circuits, 60(12), 4321-4335. Heel, J., Bindra, H. S., Louwsma, S. M., Dezzani, A. & Nauta, B.https://doi.org/10.1109/JSSC.2025.3598874

2024

Circuit with a latch having sets of inverters (2024)[Patent › Patent]. Cents, R., Ponte, J., Bindra, H. S. & Nauta, B.

Research profiles

Low Energy Circuit Design Techniques

Analog power consumption does not depend on supply voltage and unlike digital, doesn’t benefit from technology scaling. The focus of this research work is to investigate CMOS circuit design techniques for minimizing the energy consumption for a given analog operation.

Address

University of Twente

Carré (building no. 15)
Hallenweg 23
7522 NH Enschede
Netherlands

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Organisations

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