Zilverling

dr.ir. M. Ottavi (Marco)

Associate Professor
EEMCS-CS-CAES
Zilverling 5039
m.ottavi@utwente.nl
+31534897611
Business card

Marco Ottavi graduated in Electronic Engineering at the University of Rome "La Sapienza,” and obtained a doctorate in Telecommunications and Microelectronics Engineering at the University of Rome "Tor Vergata.” From 2003 to 2007, he was visiting scholar and research associate at Northeastern University in Boston (USA). In 2006 he was visiting research scholar at Sandia National Laboratories in Albuquerque (USA). In 2007 he was granted permanent residence in the United States ("green card") with the EB1 visa for "outstanding researchers.” From 2007 to 2009, he was Senior Design Engineer at Advanced Micro Devices (AMD) in Boxborough (USA). In 2009 he joined the University of Rome "Tor Vergata" as the winner of a "Rientro dei Cervelli" scholarship; since 2014, he has been Associate Professor at the same university. In 2021 he joined the Computer Architecture for Embedded Systems (CAES) group as an Associate Professor. 

Expertise

  • Computer Science

    • Memristor
    • Application
    • Models
    • Simulation
    • Design
    • Error Correction Code
    • Microprocessor
    • Computing

Organisations

My research focuses on dependable computing systems based on emerging technologies and paradigms. On these topics, I have published more than 150 contributions to international congresses and journals, of which I am also a reviewer and organizer. From 2011 to 2015, I coordinated the European project COST IC1103 MEDIAN (Manufacturable and Dependable Multicore Architectures at Nanoscale). I serve and have served as Associate Editor for IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Nanotechnology, and IEEE Nanotechnology Magazine. I am a senior member of IEEE.

Publications

Jump to: 2024 | 2023 | 2022 | 2021

2024

Divertor Tokamak Test facility project: status of design and implementation (2024)Nuclear Fusion, 64(11). Article 112015. Romanelli, F., Abate, D., Acampora, E., Agguiaro, D., Agnello, R., Agostinetti, P., Agostini, M., Aimetta, A., Albanese, R., Alberti, G., Albino, M., Alessi, E., Almaviva, S., Alonzo, M., Ambrosino, R., Andreoli, P., Angelone, M., Angelucci, M., Angioni, C., … Wu, H. S.https://doi.org/10.1088/1741-4326/ad5740Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers (2024)In 2024 IEEE 30th International Symposium on On-line Testing and Robust System Design, IOLTS 2024. IEEE. Forlin, B., Annink, E. B., Cishugi, E., Cazzaniga, C., Rech, P., Rauwerda, G., Furano, G. & Ottavi, M.https://doi.org/10.1109/IOLTS60994.2024.10616084Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer (2024)In Architecture of Computing Systems - 37th International Conference, ARCS 2024, Proceedings (pp. 127-141) (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 14842 LNCS). Springer. te Hofsté, G., Lund, A., Ottavi, M. & Lüdtke, D.https://doi.org/10.1007/978-3-031-66146-4_9Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes (2024)In 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings (Proceedings -Design, Automation and Test in Europe, DATE). IEEE. Forlin, B., Chen, K. H., Alachiotis, N., Cassano, L. & Ottavi, M.https://ieeexplore.ieee.org/document/10546790

2023

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses (2023)In 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. Palumbo, A., Ottavi, M. & Cassano, L.https://doi.org/10.1109/DFT59622.2023.10313534Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes (2023)In 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. Palumbo, A., Cassano, L., Reviriego, P. & Ottavi, M.https://doi.org/10.1109/DFT59622.2023.10313563Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs (2023)In 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. Böhmer, K., Forlin, B., Cazzaniga, C., Rech, P., Furano, G., Alachiotis, N. & Ottavi, M.https://doi.org/10.1109/DFT59622.2023.10313556Towards Dependable RISC-V Cores for Edge Computing Devices (2023)In 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS) (Proceedings - 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design, IOLTS 2023). IEEE. Nikiema, P. R., Palumbo, A., Aasma, A., Cassano, L., Kritikakou, A., Kulmala, A., Lukkarila, J., Ottavi, M., Psiakis, R. & Traiola, M.https://doi.org/10.1109/IOLTS59296.2023.10224862Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures (2023)[Working paper › Preprint]. Su, J.-H., Lu, C.-H., Lee, J. K., Coluccio, A., Riente, F., Vacca, M., Ottavi, M. & Chen, K.-H.https://doi.org/10.48550/arXiv.2303.12128Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core (2023)Journal of Low Power Electronics and Applications, 13(1). Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F., Ottavi, M. & Olivieri, M.https://doi.org/10.3390/jlpea13010002An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? (2023)In Proceedings - 2023 IEEE European Test Symposium, ETS 2023 (Proceedings IEEE European Test Symposium (ETS); Vol. 2023). IEEE. Forlin, B. E., van Huffelen, W., Cazzaniga, C., Rech, P., Alachiotis, N. & Ottavi, M.https://doi.org/10.1109/ETS56758.2023.10174076Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems (2023)[Thesis › PhD Thesis - Research UT, graduation UT]. University of Twente. Ebrahimi, H.https://doi.org/10.3990/1.9789036557603DEV-PIM: Dynamic Execution Validation with Processing-in-Memory (2023)In Proceedings - 2023 IEEE European Test Symposium, ETS 2023 (Proceedings of the European Test Workshop; Vol. 2023-May). IEEE. Bolat, A., Tugrul, Y. C., Celik, S. H., Sezer, S., Ottavi, M. & Ergin, O.https://doi.org/10.1109/ETS56758.2023.10174063Exploring Genomic Sequence Alignment for Improving Side-Channel Analysis (2023)In Computer Security – ESORICS 2023: 28th European Symposium on Research in Computer Security, The Hague, The Netherlands, September 25–29, 2023, Proceedings, Part III (pp. 203-221) (Lecture Notes in Computer Science; Vol. 14346). Springer. Uchoa, H., Arora, V., Vermoen, D., Ottavi, M. & Alachiotis, N.https://doi.org/10.1007/978-3-031-51479-1

2022

Preventing Soft Errors and Hardware Trojans in RISC-V Cores (2022)In Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). IEEE. Annink, E. B., Rauwerda, G., Hakkennes, E., Menicucci, A., Mascio, S. D., Furano, G. & Ottavi, M.https://doi.org/10.1109/DFT56152.2022.9962340Is RISC-V ready for Space? A Security Perspective (2022)In Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). IEEE. Cassano, L., Mascio, S. D., Palumbo, A., Menicucci, A., Furano, G., Bianchi, G. & Ottavi, M.https://doi.org/10.1109/DFT56152.2022.9962352RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures (2022)Electronics, 11(19). Article 2990. Coluccio, A., Ieva, A., Riente, F., Roch, M. R., Ottavi, M. & Vacca, M.https://doi.org/10.3390/electronics11192990Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability (2022)In 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE. Bala, A., Khandelwal, S., Jabir, A. & Ottavi, M.https://doi.org/10.1109/IOLTS56730.2022.9897183Low power memristive gas sensor architectures with improved sensing accuracy (2022)Journal of Computational Electronics, 21(4), 1005-1016. Khandelwal, S., Ottavi, M., Martinelli, E. & Jabir, A.https://doi.org/10.1007/s10825-022-01890-0Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer (2022)Journal of systems architecture, 128. Article 102543. Palumbo, A., Cassano, L., Luzzi, B., Hernández, J. A., Reviriego, P., Bianchi, G. & Ottavi, M.https://doi.org/10.1016/j.sysarc.2022.102543Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches (2022)IEEE transactions on very large scale integration (VLSI) systems, 30(7), 938-951. Arikan, K., Palumbo, A., Cassano, L., Reviriego, P., Pontarelli, S., Bianchi, G., Ergin, O. & Ottavi, M.https://doi.org/10.1109/TVLSI.2022.3171810Novel Applications Enabled by Memristors [Guest Editorial] (2022)IEEE Nanotechnology Magazine, 16(2), 3-3. Kvatinsky, S. & Ottavi, M.https://doi.org/10.1109/MNANO.2022.3141442Neutron irradiated perovskite films and solar cells on PET substrates (2022)Nano Energy, 93. Article 106879. De Rossi, F., Taheri, B., Bonomo, M., Gupta, V., Renno, G., Yaghoobi Nia, N., Rech, P., Frost, C., Cazzaniga, C., Quagliotto, P., Di Carlo, A., Barolo, C., Ottavi, M. & Brunetti, F.https://doi.org/10.1016/j.nanoen.2021.106879ERIC: An Efficient and Practical Software Obfuscation Framework (2022)In Proceedings - 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2022 (pp. 466-474) (Proceedings - Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2022; Vol. 2022). IEEE. Bolat, A., Celik, S. H., Olgun, A., Ergin, O. & Ottavi, M.https://doi.org/10.1109/DSN53405.2022.00053

2021

A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability (2021)ACM transactions on design automation of electronic systems, 26(6). Article 3460004. Chattopadhyay, S., Santikellur, P., Chakraborty, R. S., Mathew, J. & Ottavi, M.https://doi.org/10.1145/3460004

Research profiles

The Dependable Computing Systems Group is currently involved in the following research activity.

Current projects

TRISTAN (Together for RISc-V Technology and ApplicatioNs)

The TRISTAN project is a KDT-JU European Union-funded initiative that aims to mature and expand the European RISC-V ecosystem for the next generation of industrial hardware to compete with existing commercial alternatives. The project will cover a wide range of areas, including software tools, EDA tools, and RTL components, to ensure a complete stack based on RISC-V. TRISTAN will include several work packages to cover market requirements, the development of industrial-grade CPU and SoC building blocks, software stacks, and applications/demos. One of the key focuses of the project is to provide European digital sovereignty and democratic access to most of the RISC-V IPs. As such, a significant portion of the developed IP blocks will be made available as open-source.

Probabilistic Data Structures for Secure and Reliable RISC-V Processor

ESA Co-sponsored Research: Open Ideas Channel

The proposed research activity will investigate the potential of checkers based on probabilistic data structures within the emerging open ISA RISC-V to completely change the design paradigm for functional safety and hardware security in microprocessor architectures. On the safety side, the constant trend toward intelligent systems at the edge (such as autonomous driving vehicles but also AI on-board satellites) is pushing to adopt stringent functional safety Failure rate (FIT) goals that can only be matched by adopting fault-tolerant techniques at the microprocessor level. On the security side, there are currently several proposals for ISA extension to provide cryptographic security primitives and create trusted execution zones; however, the emergence of trust and architectural vulnerability issues requires to detect the possible presence of Hardware Trojans Horses (HTH) and exploits such as Spectre and Meltdown. Therefore there is a need to study architectural countermeasures to defuse HTHs and, at the same time, circumvent micro-architectural flaws that architectural side-channel attacks could exploit. The ambition of this project is to focus on the design of combined techniques in the RISC-V platform to address concurrently the high safety and high security emerging requirements, thus providing an overall highly dependable processor architecture. In particular, this project will explore the potential of the use of checkers based on probabilistic data structures, for example, Bloom Filters, that are usually applied to networking packets inspection and apply them to monitor the internal operation of a microprocessor core.

News on utwente.nl

This memorandum of understanding between the European Space Agency (ESA) and the University of Twente will enhance our collaboration on designing and characterizing dependable computing systems for space applications.
https://www.utwente.nl/en/eemcs/news/2024/3/1392853/formalising-collaboration-with-the-european-space-agency

Address

University of Twente

Zilverling (building no. 11), room 5039
Hallenweg 19
7522 NH Enschede
Netherlands

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