dr.ir. M. Ottavi (Marco)

TRISTAN (Together for RISc-V Technology and ApplicatioNs)

The TRISTAN project is a KDT-JU European Union-funded initiative that aims to mature and expand the European RISC-V ecosystem for the next generation of industrial hardware to compete with existing commercial alternatives. The project will cover a wide range of areas, including software tools, EDA tools, and RTL components, to ensure a complete stack based on RISC-V. TRISTAN will include several work packages to cover market requirements, the development of industrial-grade CPU and SoC building blocks, software stacks, and applications/demos. One of the key focuses of the project is to provide European digital sovereignty and democratic access to most of the RISC-V IPs. As such, a significant portion of the developed IP blocks will be made available as open-source.

Probabilistic Data Structures for Secure and Reliable RISC-V Processor

ESA Co-sponsored Research: Open Ideas Channel

The proposed research activity will investigate the potential of checkers based on probabilistic data structures within the emerging open ISA RISC-V to completely change the design paradigm for functional safety and hardware security in microprocessor architectures. On the safety side, the constant trend toward intelligent systems at the edge (such as autonomous driving vehicles but also AI on-board satellites) is pushing to adopt stringent functional safety Failure rate (FIT) goals that can only be matched by adopting fault-tolerant techniques at the microprocessor level. On the security side, there are currently several proposals for ISA extension to provide cryptographic security primitives and create trusted execution zones; however, the emergence of trust and architectural vulnerability issues requires to detect the possible presence of Hardware Trojans Horses (HTH) and exploits such as Spectre and Meltdown. Therefore there is a need to study architectural countermeasures to defuse HTHs and, at the same time, circumvent micro-architectural flaws that architectural side-channel attacks could exploit. The ambition of this project is to focus on the design of combined techniques in the RISC-V platform to address concurrently the high safety and high security emerging requirements, thus providing an overall highly dependable processor architecture. In particular, this project will explore the potential of the use of checkers based on probabilistic data structures, for example, Bloom Filters, that are usually applied to networking packets inspection and apply them to monitor the internal operation of a microprocessor core.