I work on dependable computing for resource-constrained systems, with a focus on RISC-V platforms and radiation-aware design. My approach combines experimental validation with lightweight architectural and hardwareâsoftware techniques.
Brief CV:
- Ph.D., University of Twente (2026) â dependable computing for RISC-V microcontroller-class systems
- M.Sc. Computer Science (2022), B.Sc. Electrical Engineering (2019) â UFRGS, Brazil
- Conducted research visits at TU Munich and TU Delft (while affiliated with UFRGS)
Highlights:
- 24 peer-reviewed publications
- Co-inventor of a patent on radiation-aware fault mitigation
- Co-founder of Tuentes (dependable embedded systems in radiation environments)
- Led multiple radiation testing campaigns (RADNEXT)
- Reviewer for IEEE Transactions on Computers, organizing committee member of DFTS
Organisations
Research interests:
- Dependable and fault-tolerant computing
- RISC-V architectures and embedded systems
- Radiation effects in electronics
- Hardwareâsoftware co-design
- Embedded system security
Approach and expertise:
I develop experimentally grounded methods for dependable computing, combining radiation testing with lightweight architectural techniques. My work focuses on quantifying trade-offs between reliability, performance, and resource overhead in constrained systems.
Technical experience:
- Radiation testing campaigns and experimental methodology (RADNEXT)
- Fault injection and reliability evaluation of embedded processors
- Lightweight fault-containment mechanisms for RISC-V systems
- Hardwareâsoftware co-design for dependable architectures
- Reliability-aware design space exploration
Student projects:
If you are interested in a bachelorâs or masterâs thesis related to dependable systems, RISC-V, or radiation-aware design, feel free to contact me with your CV and transcript.
Research profiles
Former Master students:
- M.H.W. Trip (2025): RawDRAM: A Minimal Memory Controller for Accessible Processing-in-Memory Experimentation on COTS DRAM
- W.H. Nijsink (2025): Improving Radiation Tolerance for Neuromorphic Processors
- J.T. Vinkenvleugel (2025): Exploring power trace capture setups for side-channel analysis using the test-vector leakage assessment on a RISC-V target
- Michiel Koenderink (2025): Designing a RERI-based error logging system for RISC-V cores
- Remco van Dijk (2024): Fault Injection Attacks on Trusted Execution for RISC-V Cores
- T.T. Smit (2024): Investigating RISC-V hardware for autonomy in space, exact emulation-based fault injection on a hardware accelerator
- L.G. Willemsen (2023): A Simple Homomorphic Obfuscation Scheme over Automorphisms
- Kevin Böhmer (2023): Radiation resilience evaluation of a Flash-based FPGA with a soft RISC-V Core
- J.J.W. Meijer (2023): Towards Future Proof Cryptographic Implementations: Side-Channel Analysis On Post-Quantum Key Encapsulation Mechanism CRYSTALS - Kyber
- Suhas Belle Lakshminarayan (2023):Â Fuzzing : A Comparison of Fuzzing Tools
- W.G.H. van Huffelen (2023): Observability of off-the-shelf microarchitectures based on the RISC-V Instruction Set Architecture
Former Bachelor students:
- M.J. Becker (2024): Evaluating the effectiveness of Test Vector Leakage Assessment when performed on Kyber running on a softcore RISC-V processor on an FPGA
- Mateusz Budnik (2023): Design and evaluation of a Ring Oscillator based Physically Unclonable Function
- Stijn Nowee (2022): Reliability analysis of Triple Modular Redundancy
Courses academic year 2025/2026
Courses in the current academic year are added at the moment they are finalised in the Osiris system. Therefore it is possible that the list is not yet complete for the whole academic year.
Courses academic year 2024/2025
Address
University of Twente
Zilverling (building no. 11), room 5054
Hallenweg 19
7522 NH Enschede
Netherlands
University of Twente
Zilverling 5054
P.O. Box 217
7500 AE Enschede
Netherlands
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