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High-frequency clocks with low phase noise become increasingly demanded. For example, the use of a higher sample rate or dynamic range for data converters (ADC/DAC) increases the requirement for clock accuracy.

My current research is then also into the design of a high performance clocking solution with ultra-low phase noise, high spectral purity, high PSRR and low power consumption while avoiding the use of expensive components to lower the burden for integration.

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University of Twente

Carré (building no. 15), room C2728
Hallenweg 23
7522 NH Enschede
Netherlands

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