Arbitrary Digital Clock Generation
The goal of this project is to generate highly accurate clocks up to a few GHz with an arbitrarily programmable frequency, exploiting digital CMOS techniques and mixed analog-digital blocks for timing correction. The core idea is to derive an arbitrarily programmable clock frequency from a fixed high-frequency reference clock by digital dividers and other digital synthesis techniques. It is known that this is possible in principle, but it is far from obvious how this can be done in a power efficient way. A key challenge is quantization or numerical rounding related to the use of a finite number of bits, leading to residual timing errors and unwanted frequency components (“spurious responses”).